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preliminary data sheet sda 9401 scarabaeus scan rate converter usi n g e mb e dd e d dram technology units edition feb. 28, 2001 6251-558-1pd
m i cr ona s 2 pre lim ina r y da ta s h e e t doc u me nt chan ge note ds 1 da t e secti on/ pa g e c h ang es c o mp ar ed to pr e v iou s is sue d e p a r tm ent 25.0 9 .98 c ha nge s to p r e v i ous i s su e v e r s io n 0 , e d i t ion 05 /98 ar e m a r k e d wi th a c han geba r hl i v ce 05.0 5 .99 p a ge 6 1 es d m ode l cd m ad ded , -1.5 k v , . .., 1, 5 k v iv ce 01.0 7 .99 p a ge 2 0 in mul t ip ic tur e m ode on ly st o p m o de = 01 1 0 po s- si b l e iv ce 26.0 4 .00 a ll pr elim inary da t a shee t v e r s ion 0 1 , edition 0 4 /0 0 up date new log o , r e m o v a l of c h a nge bar s cnp hn p d 1) . . . d s = doc u ment s t at e, com pares t o block 4 of docum ent numbe r
sda 9401 list of tables page micronas 3 preliminary data sheet 1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6 system description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6.1 input sync controller (isc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6.2 input format conversion (ifc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6.3 low data rate processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.3.1 vertical compression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 6.3.2 horizontal compression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.3.3 multipicture display. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 6.3.4 noise reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 6.3.5 noise measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.4 clock concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.5 output sync controller (osc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.5.1 hout generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 6.5.2 vout generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 6.5.3 operation mode generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 6.5.4 window generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 6.6 output format conversion (ofc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6.7 high data rate processing (hdr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.8 i2c bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 6.8.1 i2c bus slave address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 6.8.2 i2c bus format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 6.8.3 i2c bus commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 6.8.4 detailed description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 7 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 8 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 9 characteristics (assuming recommended operating conditions) . . . . . . . . . . 64 10 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 11 waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 11.1 i2c-bus timing start/stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 11.2 i2c-bus timing data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 11.3 timing diagram clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 11.4 clock circuitry diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 12 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
sda 9401 micronas 4 preliminary data sheet 1 general description the sda 9401 is a new component of the micronas megavision ? ic set in a 0.35 m embedded dram technology (field memory embedded). the sda 9401 is pin compatible to the sda 9400 (frame memory embedded). the sda 9401 comprises all main functionalities of a digital featurebox in one monolithic ic. the sda 9401 does a simple 100/120 hz interlaced (50/60 hz progressive) scan rate conversion. the scan rate converted picture can be vertically expanded. the sda 9401 has a freerunning mode, therefore features like multiple picture display (e.g. tuner scan) are possible. the noise reduction is field based. furthermore separate motion detectors for luminance and chrominance have been implemented. for automatic controlling of the noise reduction parameters a noise measurement algorithm is included, which measures the noise level in the picture or in the blanking period. in addition a spatial noise reduction is implemented, which reduces the noise even in the case of motion. the input signal can be compressed horizontally and vertically with a certain number of factors. therefore split screen modes are supported too. beside these additional functions like coloured background, windowing and flashing are implemented. 2 features two input data formats - 4:2:2 luminance and chrominance parallel (2 x 8 wires) - itu-r 656 data format (8 wires) two different representations of input chrominance data - 2?s complement code - positive dual code flexible input sync controller flexible compression of the input signal - digital vertical compression of the input signal (1.0, 1.25, 1.5, 1.75, 2.0, 3.0, 4.0) - digital horizontal compression of the input signal (1.0, 2.0, 4.0) noise reduction - motion adaptive spatial and temporal noise reduction (3d-nr) - temporal noise reduction for luminance field based - temporal noise reduction for chrominance field based - separate motion detectors for luminance and chrominance - flexible programming of the temporal noise reduction parameters - automatic measurement of the noise level (5 bit value, readable by i2c bus) tv mode detection by counting line numbers (pal, ntsc, readable by i2c bus) embedded memory - 3.2 mbit embedded dram core for field memories - 128 kbit embedded dram core for line memories
sda 9401 micronas 5 preliminary data sheet flexible clock and synchronization concept - decoupling of the input and output clock system possible scan rate conversion - simple 100/120 hz interlaced scan conversion (e.g. aabb, aa*b*b) - simple progressive scan conversion (e.g. aa*) flexible digital vertical expansion of the output signal (1.0, ... [1/32] ... , 2.0) flexible output sync controller - flexible positioning of the output signal - flexible programming of the output sync raster signal manipulations - insertion of coloured background - vertical and/or horizontal windowing with four different speed factors - flash generation - still field - support of split screen applications - multiple picture display - tuner scan (4 and 16 times for 4:3, 12 times for 16:9 tubes) - support of multi picture display with pip or front-end processor with integrated scaler (e.g. 9 times display of pip pictures, picture tracking, random pictures, still-in-moving picture, moving-in-still picture) i2c-bus control (400 khz) p-mqfp-64 package 3.3 v 5% supply voltage
sda 9401 micronas 6 preliminary data sheet 3 block diagram the sda 9401 contains the blocks, which will be briefly described below: isc - flexible input sync controller ifc - input format conversion ldr - low data rate processing (noise reduction and measurement, vertical compression, horizontal compression) mc - memory controller osc - flexible output sync controller ofc - output format conversion hdr - high data rate processing (scan rate conversion, vertical expansion) i2c - i2c bus interface pll1/2 - pll for frequency doubling lm - line memory core ed - edram core lm line memory ldr vertical, horizontal decimation noise reduction and measurement ed edram interfaces data buffer voltage control test controller mc memory controller hdr scan rate conversion vertical interpolation ifc input format conversion i2c i2c bus interface yin sda scl uvin lm line memory isc input sync controller osc output sync controller yout uvout vout hout href hin vin clk1 ofc output format conversion pll1 clock doubling pll2 clock doubling clkout x1/clk2 x2 interlaced bd9401s syncen reset
sda 9401 micronas 7 preliminary data sheet 4 pin configuration uvout2 uvout1 uvout0 uvin0 vdd2 vdd1 scl sda reset hin vin clk1 vss2 test sda 9401 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 vss1 vdd1 yout0 yout1 yout2 yout3 yout4 yout5 yout6 yout7 vss1 vdd2 uvout7 uvout6 uvout5 uvout4 uvout3 syncen vss1 vdd1 yin0 yin1 yin2 yin3 yin4 yin5 yin6 yin7 uvin7 uvin6 uvin5 uvin4 uvin3 uvin2 uvin1 vss2 vdd1 vout hout href vss1 vdd2 x1/clk2 x2 clkout vss1 interlaced pin49401 vss2 vdd2 vdd2
sda 9401 micronas 8 preliminary data sheet 5 pin description s: supply, i: input, o: output, ttl: digital (ttl) ana: analog pd: pull down pin no. name type description 2,8,24,42,55 vss1 s supply voltage ( v ss = 0 v ) 9,25,41,56 vdd1 s supply voltage ( v dd = 3.3 v ) 36,52,58 vss2 s supply voltage ( v ss = 0 v ) 35,51,53,57, 59 vdd2 s supply voltage ( v dd = 3.3 v ) 43,..,50 yin0...7 i/ttl data input y (see input data format) 31,..,34;37,..., 40 uvin0...7 i/ttl pd data input uv (for 4:2:2 parallel, see input data format) (for ccir 656, see input data format) 30 reset i/ttl system reset. the reset input is low active. in order to ensure correct operation a " power on reset " must be performed. the reset pulse must have a minimum duration of two clock periods of the system clock clk1. 23 hin i/ttl pd h-sync input (only for full ccir 656) 22 vin i/ttl pd v-sync input (only for full ccir 656) 29 syncen i/ttl synchronization enable input 21 sda i/o i 2 c-bus data line (5v ability) 20 scl i i 2 c-bus clock line (5v ability) 54 clk1 i/ttl system clock 1 17,..,10 uvout0...7 o/ttl data output uv (see output data format) 7,..,3;1;64;63 yout0...7 o/ttl data output y (see output data format) 62 href o/ttl horizontal active video output 61 vout i/ttl v-sync output 60 hout i/ttl h-sync output 18 interlaced o/ttl interlace signal for ac coupled vertical deflection 28 x1 / clk2 i/ttl crystal connection / system clock 2 27 x2 o/ana crystal connection 26 clkout o/ttl clock output (depends on i2c parameters clk11en, clk21en, see also clock concept on page 27) 19 test i/ttl test input, connect to v ss for normal operation
micronas 9 preliminary data sheet sda 9401 6 system description 6.1 input sync controller (isc) input signals the input sync controller derives framing signals from the h- and v-sync for the input data processing. the framing signals depend on different parameters and mark the active picture area. input parameter the distance between the incoming h-syncs in system clocks of clk1 must be even. signals pin number description hin 23 horizontal synchronization signal (polarity programmable, i2c bus parameter 01h hinpol, default: high active) vin 22 vertical synchronization signal (polarity programmable, i2c bus parameter 01h vinpol, default: high active) syncen 29 enable signal for hin and vin signal, low active (see also chapter input format con- version (ifc) on page 12) lines per field pixels per line nalip+pd (alpfip*2) (verpos*2) (verwidth*2) (applip*32)*clk1 (horpos* 32)*clk1 (horwidth*32)* clk1 (napipdl*4 + napipph + pd)* clk1 hin vin inpar01 pd - processing delay
micronas 10 preliminary data sheet sda 9401 input write parameter inside the sda 9401 a field detection block is necessary for the detection of an odd (a) or even (b) field. therefore the incoming h-sync h1 (delayed hin signal, delay depends on napipdl and napipph) is doubled (h2 signal). depending on the phase position of the rising edge of the vin signal an a (rising edge between h1 and h2) or b (rising edge between h2 and h1) field is detected. for proper operation of the field detection block, the vin must be delayed depending on the delay of the hin signal (h1). the figure below explains the field detection process and the functionality of the vindel parameter (inside the sda 9401 the delayed vin signal is called vd and the detected field signal is called ffd). parameter [default value] subaddress description nalip [20] 02h not active line input defines the number of lines from the v-sync to the first active line of the field alpfip [144] 03h active lines per field input defines the number of active lines naplip napipdl [0] napipph [0] 00h, 04h not active pixels per line input defines the number of pixels from the h-sync to the first active pixel of the line. the number of pixels is a combination of napipdl and napipph. applip [45] 05h active pixels per line input defines the number of active pixels pimode 1: on 0: off [0] 00h picture insert mode allows the insertion of an arbitrary picture with the horizontal and vertical width defined by verwidth and horwidth at the position defined by verpos and horpos verpos [0] 08h vertical position defines the number of lines from the first active line to the first active line of an inserted pic- ture verwidth [0] 07h vertical width defines the number of lines (vertical width) of an inserted picture horpos [0] 0ah horizontal position defines the number of pixels from the first active pixel to the first active pixel of an inserted picture horwidth [0] 09h horizontal width defines the number of pixels (hori- zontal width) of an inserted picture
micronas 11 preliminary data sheet sda 9401 field detection and vin delay input write parameter in case of non-standard signals the field order is indeterminate (e.g. aaa... , bbb... , aaabaaab..., etc.). therefore a special filtering algorithm is implemented, which can be switched on by the parameter vcrmode. the opdel parameter is used to adjust the outgoing v-sync vout in relation to the incoming delayed v-sync vin. in case of 50 hz to 100 hz interlaced scan rate conversion the opdel parameter should be greater than half the number of lines of a field plus the internal processing delay (8 lines). input write parameter the internal line counter is used to determine the information about the standard of the incoming parameter [default value] subaddress description vindel [0] 01h delay of the incoming v-sync vin (must be adjusted depending on the delay of the hin signal) fieinv 1: field a=1 0: field a=0 [0] 00h inversion of the internal field polarity vcrmode 1: on 0: off [1] 00h in case of non standard interlaced signals (vcr, play- stations) a filtering of the internal field signal can be done (can also be used for normal tv signals) parameter [default value] subaddress description opdel [170] 06h delay (in number of lines) of the internal v-sync (delayed vin) to the outgoing v-sync (vout) h1 h2 vin ffd vd clk1 (vindel * 128 + 1) * tclk1 field 1(a) vd field 2(b) ffd x x (vindel * 128 + 1) * tclk1 vin fielddet
micronas 12 preliminary data sheet sda 9401 signal. input read parameter the figure below shows applications of the picture insert mode. for this feature an additional pip circuit (e.g. sda 9388, sda 9488/89) is necessary. together with the pip iv circuit (sda 9488/89) also split screen applications like double window are possible. the compression of the inserted picture has also be done by the external pip or front-end processor. picture insert mode: application examples picture tracking, random pictures 6.2 input format conversion (ifc) input signals the sda 9401 accepts at the input side the sample frequency relations of y : (b-y) : (r-y): 4:2:2 and ccir 656. in case of ccir 656 three modes are supported (format=11 means full ccir 656 support, including h-, v-sync and field signal, format=01 means only data processing, h- and v-sync have to be added separately according pal/ntsc norm, format=10 means only data processing, h- and v-sync have to be added separately according ccir656-pal/ntsc norm). the representation of the samples of the chrominance signal is programmable as positive dual code (unsigned, parameter twoin=0) or two's complement code (twoin=1, see also chapter i2c bus format on page 45, i2c bus parameter 00h). inside the sda 9401 all algorithms assume positive dual code. parameter subaddress description tvmode 33h tv standard of the incoming signal: 1: ntsc 0: pal signals pin number description yin0...7 43, 44, 45, 46, 47, 48, 49, 50 luminance input uvin0...7 31, 32, 33, 34, 37, 38, 39, 40 chrominance input track01
micronas 13 preliminary data sheet sda 9401 input data formats x ab : x: signal component a: sample number b: bit number input sync formats the amplitude resolution for each input signal component is 8 bit, the maximum clock frequency is 27 mhz. consequently the sda 9401 is dedicated for application in high quality digital video systems. the figure below shows the generation of the internal h- and v-syncs in case of full ccir 656 mode. the h656 sync is generated after the eav. the v656 and f656 signals change synchronously with the eav timing reference code. data pin ccir 656 format = 1x format = 01 4:2:2 parallel format = 00 yin7 u 07 y 07 v 07 y 17 y 07 y 17 yin6 u 06 y 06 v 06 y 16 y 06 y 16 yin5 u 05 y 05 v 05 y 15 y 05 y 15 yin4 u 04 y 04 v 04 y 14 y 04 y 14 yin3 u 03 y 03 v 03 y 13 y 03 y 13 yin2 u 02 y 02 v 02 y 12 y 02 y 12 yin1 u 01 y 01 v 01 y 11 y 01 y 11 yin0 u 00 y 00 v 00 y 10 y 00 y 10 uvin7 u 07 v 07 uvin6 u 06 v 06 uvin5 u 05 v 05 uvin4 u 04 v 04 uvin3 u 03 v 03 uvin2 u 02 v 02 uvin1 u 01 v 01 uvin0 u 00 v 00 format hin vin yin uvin 00 pal/ntsc pal/ntsc 4:2:2 4:2:2 01 (ccir 656 only data) pa l/n tsc pal/nts c ccir 656 x 10 ccir 656 ccir 656 ccir 656 x 11 (full ccir 656) x x ccir 656 x
micronas 14 preliminary data sheet sda 9401 explanation of 656 format the figure below explains the functionality of the syncen signal. the sda 9401 needs the syncen (synchronization enable) signal, which is used to gate the yin, uvin as well as the hin and the vin signal. this is implemented for front-ends which are working with 13.5 mhz and a large output delay time for yin, uvin, hin and vin (e.g. micronas vpc32xx, output delay: 35 ns). for this application the half system clock clk1 (13.5 mhz) from the front-end should be provided at this pin. in case the front-end is working at 27.0 mhz with sync signals having delay times smaller than 25 ns, this input can be set to low level (syncen= v ss ) (e.g. micronas sda 9206, output delay: 25 ns). thus the signals yin, uvin, hin and vin are sampled with the clk1 system clock when the syncen input is low. syncen signal clk1 (27 mhz) u0 y0 v0 y1 u2 y3 yin ccir 656 interface sav eav 288 tclk1(pal) 276 tclk1(ntsc) eav 1728 tclk1(pal) 1716 tclk1(ntsc) eav x x eav x x sav x clk1 (27 mhz) yin x h656 eav v656 (e.g.) f656 (e.g.) 11111111 00000000 00000000 1fv1p 3 p 2 p 1 p 0 sav 11111111 00000000 00000000 1fv0p 3 p 2 p 1 p 0 f = 0 during field 1(a) f = 1 during field 2(b) v = 0 elsewhere v = 1 during field blanking msb lsb clk1 y0 y1 y2 y3 u0 v0 u2 v2 syncen yin uvin x x yinen uvinen y0 y1 y2 y3 u0 v0 u2 v2 x x hin/vin hinen/vinen syncen
micronas 15 preliminary data sheet sda 9401 the figure below shows the input timing and the functionality of the napipdl and napipph parameter in case of ccir 656 and 4:2:2 parallel data input format for one example. the signals hinint, yinint and uvint are the internal available sampled input signals. input timing clk1 u0 y0 v0 y1 u2 y2 v2 y3 xxx y0 y1 y2 y3 xxx u0 v0 u2 v2 xxx yin yin uvin ccir 656 interface 4:2:2 interface yinint u4 y4 y4 u4 hinint uvinint y0 u0 v0 y1 u2 y2 v2 y3 u4 u0 v0 u2 v2 y0 y1 y3 y4 u0 v0 u2 v2 yinint uvinint (napipdl* 4 + napipph + 7) * tclk1 =(0 * 4 + 2 + 7) * tclk1 = 9 tclk1 (e.g.) (napipdl* 4 + napipph + 7) * tclk1 =(0 * 4 + 3 + 7) * tclk1 = 10 tclk1 (e.g.) hin ifc01
micronas 16 preliminary data sheet sda 9401 6.3 low data rate processing the next figure shows the block diagram of the low data rate processing block. the input signal can be vertically and horizontally compressed by a limited number of factors. in case of multipicture mode the internal multipicture controller will use both compression blocks to control the different modes. furthermore the input signal can be processed by different noise reduction algorithms to reduce the noise in the signal. the noise measurement block determines the noise level of the input signal. block diagram of low data rate processing the different blocks and the corresponding parameters will be described now in more detail. 6.3.1 vertical compression the vertical compression compresses the incoming signal vertically by a constant factor given by the parameter vdecon. for the y and uv signal different filter characteristics are used. the vertical compression can be switched off. for the multipicture modes the factors vdecon 2, 3 and 4 are necessary. different filter characteristics are used for the factors 3 and 4. high quality vertical compression for double window applications is possible, because the filter characteristic is optimized for the factor 1.5. the table below shows the relation between the parameter vdecon and the compression factor. input write parameter: vdecon inside the sda 9401 the number of active lines per field depends on the chosen vertical compression factor vdecon (see also chapter output sync controller (osc) on page 29). vdecon (1ch) 0 vertical compression off 1 factor 1.25 2 factor 1.5 3 factor 1.75 4 factor 2.0 5 factor 3.0 6 factor 4.0 7 not defined line memories yin uvin y to memory uv to memory bdldr01 vertical compression horizontal compression multipicture controller spatial noise reduction temporal noise reduction noise measurement y from memory uv from memory multipic, picpos, yborder, uborder, vborder nmline, nmalg noiseme vdecon, vcsnron hdecon, hcsnron snron nron
micronas 17 preliminary data sheet sda 9401 6.3.2 horizontal compression the horizontal compression compresses the incoming signal horizontally by a constant factor. for the y and uv signal the same filter characteristics are used. the horizontal compression can be switched off. the table below shows the relation between the parameter hdecon and the compression factor. input write parameter: hdecon the applip (active pixels per line input, see also chapter input sync controller (isc) on page 9) value defines the length of an active line. inside the sda 9401 the number of active pixels per line is appl (active pixels per line) and its value depends on the chosen horizontal compression factor hdecon. the table below explains the connection between appl and applip (see also chapter output sync controller (osc) on page 29). connection between appl and applip hdecon (1ch) 00 no horizontal compression 01 factor 2 10 factor 4 11 not defined mode appl no horizontal compression (hdecon = ?00?) applip horizontal compression, factor 2 (hdecon = ?01?) (applip + 1) / 2 horizontal compression, factor 4 (hdecon = ?10?) (applip + 3) / 4 multipic > ?0? (dominant, see also chapter multipicture display on page 18) 45
micronas 18 preliminary data sheet sda 9401 6.3.3 multipicture display the figures below show the different ?multi picture modes? as they are represented on the display. fourfold multi picture twelvefold multi picture sixteenfold multi picture picpos =0 picpos =1 picpos=3 picpos =2 picpos=0 picpos=4 picpos=8 picpos=9 picpos=10 picpos=11 picpos=7 picpos=6 picpos=5 picpos=1 picpos=2 picpos=3 picpos=0 picpos=1 picpos=2 picpos=3 pi c p os = 7 pi c p os = 11 pi c p os = 15 pi c po s = 14 pi c p os = 13 picpos =12 picpos=8 picpos=9 picpos=10 pic p o s= 6 pi c p os = 5 picpos =4
micronas 19 preliminary data sheet sda 9401 the three different ?multi picture modes? can be selected by the parameter multipic. multipic=0 defines normal operation without compression. the table below explains the performed compressions depending on the ?multi picture mode? and the corresponding aspect ratio of the display. input write parameter: multipic to get a ?multi picture display? the following executions must be performed: entering a ?multi picture mode? is defined by transmitting a value multipic>0. this value of multipic must not be equal to the previous value of multipic. during the following two fields the memory will be completely filled with a constant colour defined by the parameters yborder, uborder, vborder. this colour is identical to the background and the borders of the multi picture display. the same procedure is performed when the ?multi picture mode? changes from a value multipic>0 to another value multipic>0. beginning with the following field the compressed input picture is written at the position picpos addressed via i2c-bus. the user has to address all possible positions picpos one after the other to build a complete multi picture display. in sequence, the background colour is replaced by the small pictures. the not overwritten areas of the background colour form the borders of the multi picture display. the pictures can be taken from the same source (?shots of a sequence?) or from different sources (?tuner scanning?). the actual addressed picture is moving until ?freeze mode? is activated. before entering ?multi picture mode? the ?h-and-v-freerunning mode? (see also chapter output sync controller (osc) on page 29) should be activated via the i2c bus bits houtfr and voutfr, especially when ?tuner scanning? will be performed. the ?h-and-v-freerunning mode? avoids synchronization problems of the display during changing the tuner channel. the values of alpfip (active lines per field input, see also chapter input sync controller (isc) on page 9), and alpfop (active lines per field output, see also chapter output sync controller (osc) on page 29) must be set to 144 or 121, respectively. only these standard signals corresponding to pal and ntsc systems are supported. a mixture of pal and ntsc signals is also possible. input write parameter multipic (1bh) horizontal compression vertical compression aspect ratio of the display 00 (multi picture off) normal operation, no compression 01 (fourfold) 2 : 1 2 : 1 4 : 3 10 (twelvefold) 4 : 1 3 : 1 16 : 9 11 (sixteenfold) 4 : 1 4 : 1 4 : 3 parameter subaddress description multipic 1bh defines the multi picture modes picpos 1bh position of the picture in the multi picture mode (only valid for multipic>0) yborder 17h y background value uborder 18h u background value vborder 18h v background value
micronas 20 preliminary data sheet sda 9401 interlaced conversion in multi picture mode the borders are fixed to a width of 16 pixels in horizontal direction. in vertical direction the border widths are also fixed, the number of lines, however, depends on the tv standard of the input and the display. freeze 1: on 0: off 1bh freeze mode (frozen picture) stopmode rmode raster sequence comment 0110 (aaaa mode) 0 (100/120 hz) fixed parameter subaddress description
micronas 21 preliminary data sheet sda 9401 6.3.4 noise reduction the figure below shows a block diagram of the spatial and temporal motion adaptive noise reduction (first order iir filter). the spatial noise reduction of the luminance differs from the spatial noise reduction of the chrominance. the structure of the temporal motion adaptive noise reduction is the same for the luminance as for the chrominance signal. block diagram of noise reduction 6.3.4.1 spatial noise reduction normally a spatial noise reduction reduces the resolution due to the low pass characteristic of the used filter. therefore the spatial noise reduction of the sda 9401 works adaptive on the picture content. the low pass filter process is only executed on a homogeneous area. that?s why an edge detection controls the low pass filter process and depending on the result of the edge detection the pixels for the low pass filter are chosen. the next figure shows a block diagram of the spatial noise reduction. for the uv signal only a simple spatial noise reduction algorithm (vertical and/or horizontal low pass filtering) is implemented. yin spatial noise reduction field delay yr motion detector field delay uv1 motion detector uvin tnrsel 0 1 nr01 dy duv spatial noise reduction snron vcsnron, hcsnron tnrcly, tnrhoy, tnrkoy, tnrvay, tnrfiy, nron tnrclc, tnrhoc, tnrkoc, tnrvac, tnrfic, nron ky kuv ysnr uvsnr
micronas 22 preliminary data sheet sda 9401 block diagram of spatial noise reduction input write parameter in case of vdecon>0 or hdecon>0 or multipic>0 (see also chapter vertical compression on page 16, see also chapter horizontal compression on page 17, see also chapter multipicture display on page 18) spatial noise reduction is not possible. 6.3.4.2 motion adaptive temporal noise reduction the equation below describes the behaviour of the temporal adaptive noise reduction filter. the same equation is valid for the chrominance signal. depending on the motion in the input signal, the k-factor ky (kuv) can be adjusted between 0 (no motion) and 15 (motion) by the motion detector. the k-factor for the chrominance filter can be either ky (output of the luminance motion detector, tnrsel=0) or kuv (output of the chrominance motion detector, tnrsel=1). parameter subaddress description snron 1: on 0: off 1dh spatial noise reduction of luminance signal vcsnron 1: on 0: off 1dh vertical spatial noise reduction of chrominance hcsnron 1: on 0: off 1dh horizontal spatial noise reduction of chrominance yin lm lm edge detection lp ysnr snron nr02 1 0 lm lm uvin lp lp vcsnron 1 0 hcsnron uvsnr 1 0
micronas 23 preliminary data sheet sda 9401 equation for temporal noise reduction (luminance signal) equation for temporal noise reduction (chrominance signal) the next figure shows the motion detector in more detail. temporal noise reduction can be switched off by nron (nron=0). the parameter tnrfiy/c switches between a fixed noise reduction k- factor tnrvay/c (tnrfiy/c=0) or a motion adaptive noise reduction k-factor (tnrfiy/c=1). block diagram of motion detector in case of adaptive noise reduction the k-factor depends on the detected ?motion? (see figure above). the ?motion?-ky/kuv characteristic curve (lut) is fixed inside the sda 9401, but the characteristic curve can be changed by two parameters: tnrhoy/c and tnrkoy/c. tnrhoy/c shifts the curve horizontally and tnrkoy/c shifts the curve vertically. for a fixed characteristic curve, the sensitivity of the motion detector is adjustable by tnrcly/c. lut for motion detection i yout 1 ky + 16 --------------- - ysnr yr ? ? yr + = uvout 1 k + 16 ------------ - uvsnr uv 1 ? ? uv 1 k ; + ky kuv ; ? == tnrcly/c+1 tnrhoy/c lut tnrkoy/c+1 mux 1 0 tnrvay/c mux 15 ky/uv 1 0 nron nr01 dy/uv tnrfiy/c motion motion detection 0 51015202530 motion ky/kuv 5 10 15 nr02 tnrkoy/c tnrhoy/c=0 tnrkoy/c=-1 tnrkoy/c=-8 tnrhoy/c=0 tnrkoy/c=7 tnrhoy/c=0
micronas 24 preliminary data sheet sda 9401 lut for motion detection ii parameter tnrvay/c parameter tnrhoy/c and tnrkoy/c parameter tnrcly input write parameter parameter 0 (minimum value) 15 (maximum value) tnrvay/ c strong noise reduction (not motion adaptive, ky/k=0) no noise reduction (not motion adaptive, ky/k=15) parameter range tnrhoy/c -32, ... , 31 tnrkoy/c -8, ..., 7 parameter 0 (minimum value) 15 (maximum value) tnrcly/ c maximum sensitivity for motion -> strong noise reduction minimum sensitivity for motion -> weak noise reduction parameter subaddress description tnrsel 1: separate 0: luminance motion detector 1dh switch for motion detection of temporal noise reduction of chrominance signal 51015202530 motion ky/kuv 5 10 15 nr03 tnrhoy/c tnrhoy/c=0 tnrkoy/c=-1 tnrkoy/c=-1 tnrhoy/c=-15 tnrkoy/c=-1 tnrhoy/c=15
micronas 25 preliminary data sheet sda 9401 6.3.5 noise measurement the noise measurement algorithm can be used to change the parameters of the temporal noise reduction processing depending on the actual noise level of the input signal. this is done by the i2c- bus controller which reads the noiseme value, and sends depending on this value different parameter sets to the temporal noise reduction registers of the sda 9401. the noiseme value can be interpreted as a linear curve from no noise (0) to strong noise (30). value 31 indicates an overflow status and can be handled in different ways: strong noise or measurement failed. two measurement algorithms are included, which can be chosen by the parameter nmalg. in case nmalg=1 the noise is measured during the vertical blanking period in the line defined by nmline. for nmalg=0 the noise is measured during the first active line. in both cases the value is determined by averaging over several fields. the figure below shows an example for the noise measurement. the nmline parameter determines the line, which is used in the sda 9401 for the measurement. in case of vindel=0 and nmline=0 line 3 of the field a and line 316 of the field b is chosen. in case of vindel=0 and nmline=3 line 6 of the field a and line 319 of the field b is chosen. tnrfiy/c 1: off 0: on 21h/22h switch for fixed k-factor value defined by tnrvay/c tnrvay/c 20h fixed k-factor for temporal noise reduction of lumi- nance/chrominance tnrhoy/c 21h/22h horizontal shift of the motion detector characteristic tnrkoy/c 1fh vertical shift of the motion detector characteristic tnrcly/c 1eh classification of temporal noise reduction parameter subaddress description
micronas 26 preliminary data sheet sda 9401 example of noise measurement input write parameter input read parameter parameter subaddress description nmalg 1dh noise measurement algorithm 1: measurement during vertical blanking period (measure line can be defined by nmline) 0: measurement in the first active line nmline 28h line for noise measurement (only valid for nmalg=1) parameter subaddress description noiseme 32h noise level of the input signal: 0 (no noise), ... , 30 (strong noise) [31 (strong noise or measurement failed)] nmstatus 33h signals a new value for noiseme 1: a new value can be read 0: current noise measurement not finalized (see also chapter i2c bus format on page 45) 123456 7 625 624 623 field1 (a) 313-1 314-2 315-3 316-4 317-5 318-6 319-7 312 311 310 field2 (b) pal h-sync v-sync h-sync v-sync vindel=0 nmline=0 measure nmline=3 vindel=0 nmline=0 measure nmline=3 measure measure nm01 : : : :
micronas 27 preliminary data sheet sda 9401 6.4 clock concept input signals output signals the sda 9401 supports different clock concepts. in chapter 10 (see also chapter application information on page 65) a typical application of the circuit is shown. the front-end clock is connected to clk1 input. the clkout pin is connected to the back-end and the x1/clk2 input is connected to a crystal oscillator. the next figure explains the different clock switches, which may be used for the separate modes (see also page 31, ?ingenious configurations of the hout and vout generator?). clock concept clock concept switching matrix signals pin number description clk1 54 system clock 1 input x1/clk2 28 system clock 2 input signals pin number description clkout 26 clock output clk11en (19h) clk21en (19h) clkout 01clk1 0 0 not allowed 1 x clk2_pll2 cloco clk1 x1/clk2 pll1 pll2 clk21en clk11en clkout 1 0 0 1 clk1_pll1 clk2_pll2
micronas 28 preliminary data sheet sda 9401 input write parameter clock used in block clk1_pll1 isc, ifc, ldr, ed, mc, lm, i2c clk2_pll2 osc, hdr, ed, mc, lm, ofc parameter subaddress description pll1off 1: off 0: on 02h pll 1 on or off pll1ra 09h,0ah pll range, only for test purposes pll2off 1: off 0: on 16h pll 2 on or off pll2ra 19h pll range, only for test purposes clkouton 1: enabled 0: disabled 16h output of system clock
sda 9401 micronas 29 preliminary data sheet 6.5 output sync controller (osc) output signals the output sync controller generates horizontal and vertical synchronization signals for the scan rate converted output signal. the figures below show the block diagram of the osc and the existing parameters. block diagram of osc signals pin number description hout 60 horizontal synchronization signal (polarity programmable, i2c bus parameter 14h houtpol, default: high active) vout 61 vertical synchronization signal (polarity programmable, i2c bus parameter 14h voutpol, default: high active) href 62 horizontal active video output interlaced 18 interlaced signal (can be used for ac cou- pled deflection circuits) osc01 hout generator vout generator window generator hout href vout interlaced houtpol, houtfr, applop, houtdel, napop, pplop voutpol, intmode, nalop, alpfop, lpfop windvon, windvdr, windvsp, windvst, windhon, windhdr, windhsp, windhst hin vin operation mode generator stopmode
sda 9401 micronas 30 preliminary data sheet output parameter output write parameter parameter [default value] subaddress description nalop [22] 0bh not active line output defines the number of lines from the v-sync to the first active line of the output frame alpfop [144] 0ch active lines per field output defines the number of active lines per output frame lpfop [156] 0dh lines per frame output defines the number of lines per output frame (only valid for voutfr=1) houtdel [4] 0fh hout delay defines the number of pixels from the h- sync to the first active pixel napop [0] 0eh not active pixel output defines the number of not active pixels (e.g. coloured border values) applop [45] 10h active pixels per line output defines the number of pixels per line including border pixels appl internal active pixels per line defines the number of active pixels (see also horizontal compression on page 17, applip) pplop [432] 11h, 12h pixel per line output defines the number of pixels bet- ween two consecutive h-syncs (only valid for houtfr=1) lpfop*4+1 (pplop*2)*clk2 (nalop+1)*2 (alpfop*4) (applop*16)*clk2 (houtdel*4+1)*clk2 hout (napop*4)*clk2 (appl*16)*clk2 vout inpar01
sda 9401 micronas 31 preliminary data sheet the next paragraphs describe the hout and vout generator in more detail. both generators have a so called ?locked-mode? and ?freerunning-mode?. not all combinations of the modi make sense. the table below shows ingenious configurations. ingenious configurations of the hout and vout generator 6.5.1 hout generator the hout generator has two operation modes, which can be selected by the parameter houtfr. the hout signal is active high (houtpol=0) for 64 clock cycles (x1/clk2). in the freerunning- mode the hout signal is generated depending on the pplop parameter. in the locked-mode the hout signal is locked on the incoming h-sync signal hin. the polarity of the hout signal is programmable by the parameter houtpol. the href signal marks the active part of a line. the figure below shows the timing relation of the hout and the href signal. the distance is programmable by the parameter houtdel. pd means processing delay of the internal data processing (pd=36 x1/clk2 clocks). the length of the active part is determined by the parameter applop. if the number of the active pixels (internal parameter appl, see also horizontal compression on page 17) is smaller than the number of the displayed pixels (e.g. displaying a 4:3 source on a 16:9 screen), a coloured border can be defined using the napop parameter. the border colour is defined by the parameters yborder, uborder and vborder. to avoid transition artifacts of digital filters the number of active pixels per line (parameter appl) can be symmetrically reduced using the capp parameter. the figure below shows also the internal signal alop, which marks the active pixels of the line. mode houtfr voutfr clk11en clk21en ?h-and-v-locked? 0 0 1 1 ?h-freerunning-v-locked? 1 0 1 0 ?h-and-v-freerunning? 1 1 1 0
sda 9401 micronas 32 preliminary data sheet timing diagram of output signals output write parameter 6.5.2 vout generator the vout generator has two operation modes, which can be selected by the parameter voutfr. the vout signal is active high (voutpol=0) for two output lines. in the freerunning-mode the vout signal is generated depending on the lpfop parameter. in the locked-mode the vout signal is synchronized by the incoming v-sync signal vin (means the internal vin delayed by the parameter opdel, see also input sync controller (isc) on page 9). the rmode parameter (raster mode 1: progressive, 0: interlaced) determines the scan rate conversion parameter subaddress description houtfr 1: freerun 0: locked mode 14h hout generator mode select yborder 17h y border value (four msb of the 8 bit colour) uborder 18h u border value (four msb of the 8 bit colour) vborder 18h v border value (four msb of the 8 bit colour) capp 00: k = 0 01: k = 8 10: k = 16 11: k = 24 10h reducing factor for the active pixels per line value (appl) number of active pixels per line = 16 * appl - 2*k x1/clk2 pplop * 2 tx1/clk2 e.g. 432 * 2 / 27 mhz = 32 s y0 y1 x y2 y3 y4 y5 u0 v0 x u2 v2 u4 v4 ((houtdel + 1) * 4 + pd)* tx1/clk2 ym-2 um-2 ym-1 vm-2 x x m=appl*16 href applop * 16 * tx1/clk2 e.g. 45 * 16 = 720 tx1/clk2 64 * tx1/clk2 hout yout uvout outpar01 yb yb x yb yb y0 y1 ub vb x ub vb u0 v4 ((houtdel + 1 + napop) * 4 + pd)* tx1/clk2 yb ub yb vb x x m=appl*16 yout uvout alop
sda 9401 micronas 33 preliminary data sheet mode. the figure below shows the two cases. if rmode=1, then for each incoming v-sync signal vin an outgoing v-sync signal vout has to be generated (50 hz interlaced to 50 hz progressive scan rate conversion). if rmode=0, then during one incoming v-sync signal, two vout pulses have to be generated (50 hz interlaced to 100 hz interlaced scan rate conversion). examples for vout generation depending on parameter rmode the vout signal has a delay of two clkout clocks to the hout signal or in case of interlaced a delay of a half line plus two clkout clocks. output write parameter switching from h-and-v-freerunning to h-and-v-locked mode in h-and-v-freerunning mode, generally, the phase of the generated synchronization raster has no correlation to the input raster. a hard switch from the h-and-v-freerunning mode to the h-and-v- locked mode therefore would cause visible synchronization artefacts. to avoid these problems the sda 9400 enlarges the line and the field lengths of the output sync signals hout and vout in a defined procedure to enable an unvisible synchronization of the freerunning output to the input. for vertical synchronization the maximum synchronization time is 260 ms for interlaced and 520 ms for progressive display modes. horizontal synchronization is performed in a maximum time of 50 ms. to get the best performance it is recommended to change at first the vertical and after the mentioned delay times the horizontal mode from free running to locked. parameter subaddress description voutfr 1: freerun 0: locked mode 14h vout generator mode select rmode 1: progressive 0: interlaced 14h raster mode vin rmode=1 vout rmode=0 vout
sda 9401 micronas 34 preliminary data sheet 6.5.3 operation mode generator the vout generator determines the vout signal. for proper operation of the vout generator information about the raster sequence is necessary. the parameter stopmode (static operation mode) defines the raster sequence and the scan rate conversion algorithm. the figure below explains the used wording for the following explanations. explanations of field and display raster the interlaced input signal (e.g. 50 hz pal or 60 hz ntsc) is composed of a field a (odd lines) and a field b (even lines). a n - input signal, field a at time n, b n - input signal, field b at time n the field information describes the picture content. the output signal, which could contain different picture contents (e.g. field a, field b ) can be displayed with the display raster or ? . (a n , ) - output signal, field a at time n, displayed as raster field b field a odd lines even lines frame/field frame content of picture display raster tv display raster display raster display raster ? tube, display raster odd lines even lines fieldras01
sda 9401 micronas 35 preliminary data sheet (a n , ? ) - output signal, field a at time n, displayed as raster ? ((a*) n , ? ) - output signal, field a raster interpolated into field b at time n, displayed as raster ? (a n b n-1 , + ?=?= output signal, frame ab at time n, progressive the table below describes the different scan rate conversion algorithms and the corresponding raster sequences. the delay between the input field and the corresponding output fields depends on the opdel parameter and the default value for the delay is an half input field. the interlaced signal can be used for ac-coupled deflections. depending on the parameter intmode the value of this signal will be generated. the table below shows also the definition of this signal. explanation of operation mode timing s tatic operation modes input field a input field b stopmode scan rate conversion algorithm output field a n phase 0 output field b n phase 1 output field c n phase 2/0 output field d n phase 3/1 rmode 0000 not defined xxxx0 0001 aa*b*b mode i interlaced (a*) n , intmode(3) a n , intmode(0) b n , intmode(1) (b*) n , intmode(2) 0 0010 aabb mode i interlaced a n , intmode(0) a n , intmode(0) b n , intmode(1) b n , intmode(1) 0 0100 multipicture mode i a n , intmode(0) a n , intmode(0) a n , intmode(0) a n , intmode(0) 0 0101 multipicture mode ii b n-1 , intmode(1) b n-1 , intmode(1) b n , intmode(1) b n , intmode(1) 0 0110 aaaa mode a n , intmode(0) a n , intmode(0) a n , intmode(0) a n , intmode(0) 0 0111 bbbb mode b n-1 , intmode(0) b n-1 , intmode(0) b n , intmode(0) b n , intmode(0) 0 1000 not defined xxxx0 osc02 a n b n time input fields a n phase 0 b n phase 1 c n phase 2/0 d n phase 3/1 output fields b n-1 , a n fields available in the internal field stores a n-1 , b n-1 a n , b n opdel lines
sda 9401 micronas 36 preliminary data sheet the table below shows all possible display raster sequences for the different static operation modes and the line per field value between two consecutive output v-syncs. it is assumed, that in case of freerunning-mode lpfop=156 and in the locked mode the number of lines of the incoming field is 312.5. display raster sequence for rmode=1 (progressive) display raster sequence for rmode=0 (interlaced) 1001 aa*b*b mode ii interlaced (b*) n-1 , intmode(2) b n-1 , intmode(1) a n+1 , intmode(0) (a*) n+1 , intmode(3) 0 1010 aabb mode ii interlaced b n-1 , intmode(1) b n-1 , intmode(1) a n+1 , intmode(0) a n+1 , intmode(0) 0 1011,11xxnot definedxxxx0 0000 not defined xxxx1 0001 aa* mode i pro- gressive (a n a* n , ? ) (b* n b n , ? ) 1 0010 not defined xxxx1 0101 aa* mode ii pro- gressive (a n a* n , ? ) (a n a* n , ? ) 1 0111 b*b mode progres- sive (b n-1 b* n-1 , ? ) (b n b* n , ? ) 1 0011,0100, 0110 not definedxxxx1 1000 test mode (motion adaptive mode interlaced, dl) a n a* n ? ? ? ) b* n b n , a+b/ ? ) 1 1xxx not defined xxxx1 display raster sequence 1. to 2. 2. to 3. (1.) ? 625 625 display raster sequence 1. to 2. 2. to 3. 3. to 4. 4. to 5.(1.) 312 313 312 313 input field a input field b stopmode scan rate conversion algorithm output field a n phase 0 output field b n phase 1 output field c n phase 2/0 output field d n phase 3/1 rmode
sda 9401 micronas 37 preliminary data sheet output write parameter 6.5.4 window generator the figures below show the functionality of the horizontal and/or vertical window function. the actual tv display can be overwritten with a constant value (defined by yborder, uborder, vborder), which is called ?closing? or the constant value can be overwritten with the actual tv signal, which is called ?opening?. for the generation some parameters exist, which will be explained in more detail afterwards. examples for window feature 313 312 313 312 312 312.5 313 312.5 313 312.5 312 312.5 ??? test mode only) 625.5 624.5 625.5 624.5 parameter subaddress description stopmode 12h static operation modes intmode 13h, 14h free programmable interlaced signal for ac-cou- pled deflection stages display raster sequence 1. to 2. 2. to 3. 3. to 4. 4. to 5.(1.) window
sda 9401 micronas 38 preliminary data sheet the feature can be enabled by the parameter windhon/windvon. the parameter windhst/ windvst defines the status of the window (opened or closed). closed means, that only a constant value is displayed, opened means, that the full tv is displayed. the parameter windhdr/ windvdr defines, what can be done with the window (open the window, close the window). output write parameter: windhst/windvst and windhdr/windvdr with each enabling of the window function by the windhon/windvon parameter, the status of the window will be as defined by the table above, that means the windhst/windvst parameter is only once interpreted after enabling the window function. to change afterwards the status from ?window is close? to ?window is open? or vice versa only the windhdr/windvdr has to be toggled. if for example the status windhst/windvst=0 and the windhdr/windvdr=0 the window is closed and will be open after enabling the feature by setting the parameter windhon/ windvon=1. to close the window only the parameter windhdr/windvdr has to be set to 1. again to open the window windhdr/windvdr has to be set to 0. for example: after switching on the tv set, the customer should see the window closed and afterwards the window should be opened. therefore the windhst/windvst has to be set to ?0?, the windhdr/ windvdr has to be set to ?1? and the windhon/windvon has to be set to ?1?. so the customer will see first a screen with a colour defined by the i2c parameters yborder, uborder and vborder. then the windhdr/windvdr has to be set to ?0?, that means the window will be open and the customer will see the chosen tv channel. the speed of closing or opening the window can be defined by the parameter windhsp/ windvsp. the tables below explain the using of these parameters. output write parameter: windhsp windhst/ windvst description windhdr/ windvdr description 0 window is closed 0 open the window 0 window is closed 1 window remains closed 1 window is opened 0 window remains open 1 window is opened 1 close the window windhsp freerun mode locked mode time to close/ open (e.g. 720 active pixel, 10ms per output field) 00 pplop/256 distance/512 ~4s 01 pplop/128 distance/256 ~2s 10 pplop/64 distance/128 ~1s
sda 9401 micronas 39 preliminary data sheet distance: number of pixels in system clocks x1/clk2 between two output h-syncs time to close = time(field) * number of active pixels / (distance/512) e.g. time to close = 10 ms * 720 / (864/512) = 4,26 s time to close = time(field) * number of active pixels / (pplop/128) output write parameter: windvsp lpfip: lines per field of the input signal - amount of lines between two input v-syncs time to close = time(field(interlaced)/frame(progressive)) * number of active lines / (lpfip/256) e.g. time to close = 10 ms * 576 / (312/256) = 4.7 s time to close = time(field) * number of active lines / (lpfop/128) output write parameter 11 pplop/32 distance/64 ~0.5s windvsp freerun mode locked mode time to close/ open (e.g. 576 active lines, 10ms per output field) 00 lpfop/128 lpfip/256 ~5s 01 lpfop/64 lpfip/128 ~2s 10 lpfop/32 lpfip/64 ~1s 11 lpfop/16 lpfip/32 ~0.5s parameter subaddress description windvon 1: on 0: off 15h vertical window feature on or off windvdr 1: close window 0: open window 15h direction of the vertical window feature windvst 1: window is opened 0: window is closed 15h status of the vertical window feature after enabling the window feature windvsp 15h speed of the vertical window feature windhsp freerun mode locked mode time to close/ open (e.g. 720 active pixel, 10ms per output field)
sda 9401 micronas 40 preliminary data sheet 6.6 output format conversion (ofc) output signals the sda 9401 supports at the output side only the sample frequency relations of y : (b-y) : (r-y): 4:2:2. the representation of the samples of the chrominance signal is programmable as positive dual code (unsigned, parameter twoout=0) or two's complement code (twoout=1, see also i2c bus format on page 45, i2c bus parameter 17h). output data format windhon 1: on 0: off 16h horizontal window feature on or off windhdr 1: close window 0: open window 16h direction of the horizontal window feature windhst 1: window is opened 0: window is closed 16h status of the horizontal window feature after enabling the window feature windhsp 16h speed of the horizontal window feature flashon 1: on 0: off 17h flash of the tv signal (after each output v-sync the tv signal or the constant background value defined by yborder, uborder, vborder is displayed) signals pin number description yout0...7 7, 6, 5, 4, 3, 1, 64, 63 luminance output uvout0...7 17, 16, 15, 14, 13, 12, 11, 10 chrominance output data pin 4:2:2 parallel yin7 y 07 y 17 yin6 y 06 y 16 yin5 y 05 y 15 yin4 y 04 y 14 yin3 y 03 y 13 yin2 y 02 y 12 yin1 y 01 y 11 yin0 y 00 y 10 parameter subaddress description
sda 9401 micronas 41 preliminary data sheet x ab: x: signal component a: sample number b: bit number 6.7 high data rate processing (hdr) the output signal can be vertically expanded. the expansion as well as the different scan rate conversion algorithms are processed in the hdr block. for the vertical expansion line memories are used. if the operation frequency x1/clk2 is higher than 27 mhz plus 10%, the line memories will not work correctly any more. in this case only simple processing will be possible. simple processing means, that the vertical expansion must be disabled. the table below defines the internal expansion factor zoom depending on the rmode and verint parameter. output write parameter: verint the reachable expansion factors are listed in the table below in case of vdecon=0 and vdecon=2 (vertical compression of the input signal with factor 1.0 and 1.5). uvin7 u 07 v 07 uvin6 u 06 v 06 uvin5 u 05 v 05 uvin4 u 04 v 04 uvin3 u 03 v 03 uvin2 u 02 v 02 uvin1 u 01 v 01 uvin0 u 00 v 00 verint rmode zoom i2c-bus parameter 0 2*(verint+1) i2c-bus parameter 1 (verint+1) data pin 4:2:2 parallel
sda 9401 micronas 42 preliminary data sheet examples of reachable expansion factors 100/120 hz interlaced rmode=0 50/60 hz progressive rmode=1 real vertical expansion factor real vertical expansion factor verint zoom zoom vdecon=0 vdecon=2 63 128 64 1.00 0.75 62 126 63 1.02 0.76 61 124 62 1.03 0.77 60 122 61 1.05 0.79 59 120 60 1.07 0.80 58 118 59 1.08 0.81 57 116 58 1.10 0.83 56 114 57 1.12 0.84 55 112 56 1.14 0.86 54 110 55 1.16 0.87 53 108 54 1.19 0.89 52 106 53 1.21 0.91 51 104 52 1.23 0.92 50 102 51 1.25 0.94 49 100 50 1.28 0.96 48 98 49 1.31 0.98 47 96 48 1.33 1.00 46 94 47 1.36 1.02 45 92 46 1.39 1.04 44 90 45 1.42 1.07 43 88 44 1.45 1.09 42 86 43 1.49 1.12 41 84 42 1.52 1.14 40 82 41 1.56 1.17 39 80 40 1.60 1.20 38 78 39 1.64 1.23 37 76 38 1.68 1.26 36 74 37 1.73 1.30 35 72 36 1.78 1.33 34 70 35 1.83 1.37 33 68 34 1.88 1.41 32 66 33 1.94 1.45 31 64 32 2.00 1.50 30 62 31 2.06 1.55 29 60 30 2.13 1.60 28 58 29 2.21 1.66 27 56 28 2.29 1.71
sda 9401 micronas 43 preliminary data sheet the parameter vpan can be used to select the start line of the expansion. to expand the upper part of the incoming signal with the factor 2.0, vpan should be set to zero. to expand the lower part, vpan should be equal to 144. that means in case of vpan=0 the first used line is line 1 and in case of vpan=144 the first used line is line 144. dependent on the parameter verint a certain number of input lines of the input field is required. therefore not all vpan values are allowed. the formula below can be used to calculate the maximum allowed vpan value depending on the chosen verint value. calculation of maximum vpan value 26 54 27 2.37 1.78 25 52 26 2.46 1.85 24 50 25 2.56 1.92 23 48 24 2.67 2.00 22 46 23 2.78 2.09 21 44 22 2.91 2.18 20 42 21 3.05 2.29 19 40 20 3.20 2.40 18 38 19 3.37 2.53 17 36 18 3.56 2.67 16 34 17 3.76 2.82 15 32 16 4.00 3.00 14 30 15 4.27 3.20 13 28 14 4.57 3.43 12 26 13 4.92 3.69 11 24 12 5.33 4.00 10 22 11 5.82 4.36 920106.404.80 8 18 9 7.11 5.33 7 16 8 8.00 6.00 6 14 7 9.14 6.86 5 12 6 10.67 8.00 4 10 5 12.80 9.60 3 8 4 16.00 12.00 2 6 3 21.33 16.00 1 4 2 32.00 24.00 0 2 1 64.00 48.00 100/120 hz interlaced rmode=0 50/60 hz progressive rmode=1 real vertical expansion factor real vertical expansion factor verint zoom zoom vdecon=0 vdecon=2 vpanmax 2 alpfop 1 verint 1 + ? 64 ----------------------------------- - ? =
sda 9401 micronas 44 preliminary data sheet floor symbol means: take only integer part of x output write parameter parameter subaddress description verint 13h vertical expansion factor vpan 1ah vertical adjustment of the output picture x
micronas 45 preliminary data sheet sda 9401 6.8 i2c bus 6.8.1 i2c bus slave address write adress: bch read adress: bdh 6.8.2 i2c bus format the sda 9401 i 2 c bus interface acts as a slave receiver and a slave transmitter and provides two different access modes (write, read). all modes run with a subaddress auto increment. the interface supports the normal 100 khz transmission speed as well as the high speed 400 khz transmission. write: s: start condition a: acknowledge p: stop condition na: not acknowledge read: the transmitted data are internally stored in registers. the master has to write a don?t care byte to the subaddress ffh (store command) to make the register values available for the sda 9401. to have a defined time step, where the data will be available, the data are made valid with the incoming v-sync vin or with the next opstart pulse, which is an internal signal and indicates the start of a new output cycle. the subaddresses, where the data are made valid with the vin signal are indicated in the overview of the subaddresses with ?vi?, where the data are made valid with the opstart are indicated with ?os?. the i2c parameter vistatus and osstatus (subaddress 33h) reflect the state of the register values. if these bits are read as ?0?, then the store command was sent, but the data aren?t made available yet. if these bits are ?1? then the data were made valid and a new write or read cycle can start. the bits vistatus and osstatus may be checked before writing or reading new data, otherwise data can be lost by overwriting. furthermore the bit nmstatus (status of noise measurement: noiseme). nmstatus signalizes a new value for noiseme. so if nmstatus is read as ?0? the current noise measurement has not 10111100 10111101 s10111100a subaddress a data byte a ***** ap s10111100a subaddress as10111101a data byte a data byte na p
micronas 46 preliminary data sheet sda 9401 been finalized. if the nmstatus is read as ?1? a new noise measurement value can be read. after switching on the ic, all bits of the sda 9401 are set to defined states. particularly : r/w: r - read register; w - write register; r/w - read and write register; take over: vi - take over with vin; os- take over with opstart reading the ?read only? register 32h must be followed by reading the ?read only? register 33h. subaddress default value r/w take over subaddress default value r/w take over 00 11h w vi 15 00h w os 01 00h w vi 16 04h w os 02 50h w vi 17 14h w os 03 90h w vi 18 88h w os 04 00h w vi 19 0ch w os 05 b4h w vi 1a 00h w os 06 aah w vi 1b 00h w vi 07 00h w vi 1c 01h w vi 08 00h w vi 1d 03h w vi 09 00h w vi 1e ffh w vi 0a 00h w vi 1f 00h w vi 0b 16h w os 20 ffh w vi 0c 90h w os 21 02h w vi 0d 9ch w os 22 02h w vi 0e 00h w os 23...27 not used 0f 04h w os 28 22h w vi 10 b4h w os 29...31 not used 11 b0h w os 32 r 12 90h w os 33 r 13 3fh w os 34...fe not used 14 00h w os ff w
micronas 47 preliminary data sheet sda 9401 6.8.3 i2c bus commands subadd. (hex.) data byte d7 d6 d5 d4 d3 d2 d1 d0 00 format1 isc/ifc format0 isc/ifc fieinv isc vcrmode isc pimode isc napipph1 isc napipph0 isc twoin isc/ifc 01 vindel5 isc vindel4 isc vindel3 isc vindel2 isc vindel1 isc vindel0 isc vinpol isc hinpol isc 02 nalip5 isc nalip4 isc nalip3 isc nalip2 isc nalip1 isc nalip0 isc pll1off pll1 refresh mc 03 alpfip7 isc alpfip6 isc alpfip5 isc alpfip4 isc alpfip3 isc alpfip2 isc alpfip1 isc alpfip0 isc 04 napipdl7 isc napipdl6 isc napipdl5 isc napipdl4 isc napipdl3 isc napipdl2 isc napipdl1 isc napipdl0 isc 05 applip5 isc applip4 isc applip3 isc applip2 isc applip1 isc applip0 isc xx 06 opdel7 isc opdel6 isc opdel5 isc opdel4 isc opdel3 isc opdel2 isc opdel1 isc opdel0 isc 07 verwidth7 isc verwidth6 isc verwidth5 isc verwidt4 isc verwidth3 isc verwidth2 isc verwidth1 isc verwidth0 isc 08 verpos7 isc verpos6 isc verpos5 isc verpos4 isc verpos3 isc verpos2 isc verpos1 isc verpos0 isc 09 horwidth5 isc horwidth4 isc horwidth3 isc horwidth2 isc horwidth1 isc horwidt0 isc pll1ra1 pll1 pll1ra0 pll1 0a horpos5 isc horpos4 isc horpos3 isc horpos2 isc horpos1 isc horpos0 isc pll1ra3 pll1 pll1ra2 pll1 0b nalop7 osc nalop6 osc nalop5 osc nalop4 osc nalop3 osc nalop2 osc nalop1 osc nalop0 osc 0c alpfop7 osc alpfop6 osc alpfop5 osc alpfop4 osc alpfop3 osc alpfop2 osc alpfop1 osc alpfop0 osc 0d lpfop7 osc lpfop6 osc lpfop5 osc lpfop4 osc lpfop3 osc lpfop2 osc lpfop1 osc lpfop0 osc 0e napop7 osc napop6 osc napop5 osc napop4 osc napop3 osc napop2 osc napop1 osc napop0 osc 0f houtdel7 osc houtdel6 osc houtdel5 osc houtdel4 osc houtdel3 osc houtdel2 osc houtdel1 osc houtdel0 osc 10 applop5 osc applop4 osc applop3 osc applop2 osc applop1 osc applop0 osc capp1 osc capp0 osc 11 pplop7 osc pplop6 osc pplop5 osc pplop4 osc pplop3 osc pplop2 osc pplop1 osc pplop0 osc 12 pplop8 osc stopmode3 osc stopmode2 osc stopmode1 osc stopmode0 osc 000 13 intmode3 osc intmode2 osc verint5 osc verint4 osc verint3 osc verint2 osc verint1 osc verint0 osc 14 intmode1 osc intmode0 osc 0 rmode osc voutfr osc houtfr osc voutpol osc houtpol osc 15 windvon osc windvdr osc windvst osc windvsp1 osc windvsp0 osc 000
micronas 48 preliminary data sheet sda 9401 x = don?t care isc - input sync controller block ifc - input format conversion block osc - output sync controller block ofc - output format conversion block ldr - low data rate block hdr - high data rate block mc - memory controller pll1 - clock doubling block 1 pll2 - clock doubling block 2 16 windhon osc windhdr osc windhst osc windhsp1 osc windhsp0 osc clkouton pll2 pll2off pll2 x 17 yborder3 ofc/ldr yborder2 ofc/ldr yborder1 ofc/ldr yborder0 ofc/ldr flashon ofc twoout ofc 00 18 uborder3 ofc/ldr uborder2 ofc/ldr uborder1 ofc/ldr uborder0 ofc/ldr vborder3 ofc/ldr vborder2 ofc/ldr vborder1 ofc/ldr vborder0 ofc/ldr 19 pll2ra3 pll2 pll2ra2 pll2 pll2ra1 pll2 pll2ra0 pll2 clk21en pll2 clk11en pll2 00 1a vpan7 mc vpan6 mc vpan5 mc vpan4 mc vpan3 mc vpan2 mc vpan1 mc vpan0 mc 1b multipic1 ldr/isc multipic0 ldr/isc picpos3 ldr/mc picpos2 ldr/mc picpos1 ldr/mc picpos0 ldr/mc freeze mc 0 1c vdecon2 ldr vdecon1 ldr vdecon0 ldr hdecon1 ldr/isc hdecon0 ldr/isc 001 1d nron ldr/mc snron ldr vcsnron ldr hcsnron ldr 00 tnrsel ldr nmalg ldr 1e tnrcly3 ldr tnrcly2 ldr tnrcly1 ldr tnrcly0 ldr tnrclc3 ldr tnrclc2 ldr tnrclc1 ldr tnrclc0 ldr 1f tnrkoy3 ldr tnrkoy2 ldr tnrkoy1 ldr tnrkoy0 ldr tnrkoc3 ldr tnrkoc2 ldr tnrkoc1 ldr tnrkoc0 ldr 20 tnrvay3 ldr tnrvay2 ldr tnrvay1 ldr tnrvay0 ldr tnrvac3 ldr tnrvac2 ldr tnrvac1 ldr tnrvac0 ldr 21 tnrhoy5 ldr tnrhoy4 ldr tnrhoy3 ldr tnrhoy2 ldr tnrhoy1 ldr tnrhoy0 ldr tnrfiy ldr 0 22 tnrhoc5 ldr tnrhoc4 ldr tnrhoc3 ldr tnrhoc2 ldr tnrhoc1 ldr tnrhoc0 ldr tnrfic ldr 0 28 nmline4 ldr nmline3 ldr nmline2 ldr nmline1 ldr nmline0 ldr 01x 32 noisme4 ldr noisme3 ldr noiseme2 ldr noiseme1 ldr noiseme0 ldr version2 version1 version0 33 xxx tvmode ldr vistatus osstatus x nmstatus ff xxxxxxxx
micronas 49 preliminary data sheet sda 9401 6.8.4 detailed description default values are underlined. subaddress 00 bit name function d7...d6 format input format: 11: full ccir 656 10: ccir 656 only data, h- and v-sync according ccir656 01: ccir 656 only data, h- and v-sync according pal/ntsc 00: 4:2:2 d5 fieinv field polarity inversion: 1: field a=1, field b=0 0: field a=0, field b=1 d4 vcrmode input filtering of the incoming field signal: 1: on 0: off d3 pimode picture insert mode (see verwidth, verpos, horwidth, horpos): 1: on 0: off d2...d1 napipph (lsbs of naplip) number of not active pixels from external hin to the input data in system clocks of clk1: number(hin to input data) = (napipdl*4+napipph+8) [napipph = 0 ] d0 twoin chrominance input format: 1: 2?s complement input (-128...127) 0: unsigned input (0...255) inside the sda 9401 the data are always processed as unsigned data subaddress 01 bit name function d7...d2 vindel vin input delay: delay(vin to internal v-sync) = (128 * vindel + 1)*tclk1 [vindel = 0 ] d1 vinpol vin polarity: 1: low active 0: high active d0 hinpol hin polarity: 1: low active 0: high active
micronas 50 preliminary data sheet sda 9401 subaddress 02 bit name function d7...d2 nalip number of not active lines per field in the input data stream: not active lines = nalip+3 [nalip= 20 ] d1 pll1off pll1 switch: 1: off 0: on d0 refresh internal refresh: 1: on 0: off subaddress 03 bit name function d7...d0 alpfip number of active lines per field in the input data stream: active lines = alpfip * 2 [alpfip=144 ] subaddress 04 bit name function d7...d0 napipdl (msbs of naplip) number of not active pixels from hin to the input data in system clocks of clk1: number(hin to input data) = (4 * napipdl + napipph + 8) [napipdl= 0 ] subaddress 05 bit name function d7...d2 applip number of active pixels per line in the input data stream in system clocks of clk1: active pixels = applip*32 [applip = 45 ] inside the sda 9401 the number of active pixels per line is appl*32, with appl = applip, mulitpic = 0 and hdecon = 0 (applip + 1)/2, multipic = 0 and hdecon = 1 (applip + 3)/4, multipic = 0 and hdecon = 2 45, multipic > 0 d1...d0 x x
micronas 51 preliminary data sheet sda 9401 subaddress 06 bit name function d7...d0 opdel output processing delay (in number of lines): delay(vin to vout) = (opdel + 1) * tline [opdel = 170 ] subaddress 07 bit name function d7...d0 verwidth vertical width of inserted picture in input lines: vertical width = (2 * verwidth) [verwidth = 0 ] subaddress 08 bit name function d7...d0 verpos vertical position of inserted picture in input lines: vertical position = (2 * verpos) + nalip + 3 [verpos = 0 ] subaddress 09 bit name function d7...d2 horwidth horizontal width of inserted picture in system clocks of clk1: horizontal width = (32 * horwidth) [horwidth = 0 ] d1...d0 pll1ra(1...0) pll1 range, only for test purposes [ppl1ra=0 ] subaddress 0a bit name function d7...d2 horpos horizontal position of inserted picture in system clocks of clk1: horizontal position = (32 * horpos) + (4 * napipdl + napipph + 8) [horpos = 0 ] d1...d0 pll1ra(3...2) pll1 range, only for test purposes [ppl1ra=0 ]
micronas 52 preliminary data sheet sda 9401 subaddress 0b bit name function d7...d0 nalop number of not active lines per frame in the output data stream: not active lines = 2 * (nalop + 1) [nalop= 22] subaddress 0c bit name function d7...d0 alpfop number of active lines per output frame: active lines = 4 * alpfop [alpfop= 144 ] subaddress 0d bit name function d7...d0 lpfop number of lines per output frame (only valid for voutfr=1): number of lines = 4 * lpfop + 1 [lpfop = 156 ] subaddress 0e bit name function d7...d0 napop number of not active pixels (coloured border values) from external href to the first active pixel of the output data stream in system clocks of x1/ clk2: distance(href to output data) = (4 * napop) [napop = 0 ] subaddress 0f bit name function d7...d0 houtdel hout delay: delay(hout to href) = (4 * (houtdel + 1) + 36) *tx1/clk2 [houtdel = 4 ]
micronas 53 preliminary data sheet sda 9401 subaddress 10 bit name function d7...d2 applop number of active pixels per line (including coloured border values and data) in the output data stream in system clocks of x1/clk2 (length of href): active pixels = 16 * applop [applop = 45 ] d1...d0 capp reduces the active pixels per line (appl) at the output side: active pixels per line at the output side in system clocks of x1/clk2 = 16 * appl - 2 * k k = 24: capp = 11 16: capp = 10 8: capp = 01 0: capp = 00 subaddress 11 bit name function d7...d0 pplop(7...0) number of pixels between two output h-syncs hout (only valid for houtfr=1) in system clocks of x1/clk2 (bit 7 to 0): number of pixels = 2 * pplop [pplop = 432 ] subaddress 12 bit name function d7 pplop(8) number of pixels between two output h-syncs hout (only valid for houtfr=1) in system clocks of x1/clk2 (bit 8): number of pixels = 2 * pplop [pplop = 432 ] d6...d3 stopmode static operation modes (see also operation mode generator on page 34): 0010: aabb mode i interlaced d2...d0 should be set to 000 subaddress 13 bit name function d7...d6 intmode(3...2) free programmable interlaced signal for ac coupled deflection stages (bit 3 and bit 2) [intmode3...2 = 0 ]
micronas 54 preliminary data sheet sda 9401 d5...d0 verint vertical expansion factor (see also high data rate processing (hdr) on page 41): 63: no vertical expansion : 47: vertical expansion with factor 1.5 : 31: vertical expansion with factor 2 : subaddress 14 bit name function d7...d6 intmode(1...0) free programmable interlaced signal for ac coupled deflection stages (bit 1 and bit 0) [intmode1...0 = 0 ] d5 should be set to 0 d4 rmode raster mode: 1: progressive 0: interlaced d3 voutfr vout generator: 1: freerunning mode 0: locked mode d2 houtfr hout generator 1: freerunning mode 0: locked mode d1 voutpol vout (exsyn=0), vext (exsyn=1) polarity: 1: low active 0: high active d0 houtpol hout (exsyn=0), hext (exsyn=1) polarity: 1: low active 0: high active subaddress 15 bit name function d7 windvon vertical window: 1: on 0: off d6 windvdr 1: close the vertical window 0: open the vertical window subaddress 13 bit name function
micronas 55 preliminary data sheet sda 9401 d5 windvst status of vertical window after entering vertical window mode: 1: window is opened 0: window is closed d4...d3 windvsp speed of vertical window (see also window generator on page 37): 11: very fast 10: fast 01: medium 00: slow d2...d0 should be set to 000 subaddress 16 bit name function d7 windhon horizontal window: 1: on 0: off d6 windhdr 1: close the horizontal window 0: open the horizontal window d5 windhst status of horizontal window after entering horizontal window mode: 1: window is opened 0: window is closed d4...d3 windhsp speed of horizontal window (see also window generator on page 37): 11: very fast 10: fast 01: medium 00: slow d2 clkouton output of system clock clkout: 1: enabled 0: disabled d1 pll2off pll2 switch: 1: off 0: on d0 x x subaddress 17 bit name function d7...d4 yborder y border value (yborder(3) yborder(2) yborder(1) yborder(0) 0 0 0 0 = 00010000 = 16), yborder defines the 4 msb?s of a 8 bit value subaddress 15 bit name function
micronas 56 preliminary data sheet sda 9401 d3 flashon flash of output picture: 1: on 0: off d2 twoout chrominance output format: 1: 2?s complement input (-128...127) 0: unsigned input (0...255) inside the sda 9401 the data are always processed as unsigned data d1...d0 should be set to 00 subaddress 18 bit name function d7...d4 uborder u border value (uborder(3) uborder(2) uborder(1) uborder(0) 0 0 0 0 = 10000000 = 128), uborder defines the 4 msb?s of a 8 bit value d3...d0 vborder v border value (vborder(3) vborder(2) vborder(1) vborder(0) 0 0 0 0 = 10000000 = 128), vborder defines the 4 msb?s of a 8 bit value subaddress 19 bit name function d7...d4 pll2ra pll2 range, only for test purposes [ppl2ra=0 ] d3 clk21en pll2 input signal (see also clock concept on page 27): 1: external clk1 0: external x1/clk2 d2 clk11en internal clock switch for clkout (see also clock concept on page 27 ): 1: pll2 output 0: external clk1 d1...d0 should be set to 00 subaddress 1a bit name function d7...d0 vpan vertical adjustment of the output picture [vpan = 0 ] subaddress 17 bit name function
micronas 57 preliminary data sheet sda 9401 subaddress 1b bit name function d7...d6 multipic multipicture modes: 11: sixteenfold 10: twelvefold 01: fourfold 00: off (in case of multipic>0, spatial and temporal noise reduction as well as the motion detection for scan rate conversion are disabled) d5...d2 picpos position for the picture in the multipicture mode (only valid for multipic > 0, see also multipicture display on page 18) [picpos = 0 ] d1 freeze freeze mode (frozen picture): 1: on 0: off d0 should be set to 0 subaddress 1c bit name function d7...d5 vdecon vertical decimation of the input data stream: 111: not used 110: factor 4.0 101: factor 3.0 100: factor 2.0 011: factor 1.75 010: factor 1.5 001: factor 1.25 000: off (in case of vdecon>0, spatial noise reduction as well as the motion detection for scan rate conversion are disabled) d4...d3 hdecon horizontal decimation of the input data stream: 11: not used 10: factor 4.0 01: factor 2.0 00: off (in case of hdecon>0, spatial noise reduction as well as the motion detection for scan rate conversion are disabled) d2...d0 should be set to 001
micronas 58 preliminary data sheet sda 9401 subaddress 1d bit name function d7 nron temporal noise reduction of luminance and chrominance: 1: enabled 0: disabled d6 snron spatial noise reduction of luminance: 1: enabled 0: disabled d5 vcsnron vertical spatial noise reduction of chrominance: 1: enabled 0: disabled d4 hcsnron horizontal spatial noise reduction of chrominance: 1: enabled 0: disabled d3...d2 should be set to 00 d1 tnrsel motion detection of temporal noise reduction of chrominance: 1: separate motion detector 0: luminance motion detector d0 nmalg noise measurement algorithm: 1: measurement during vertical blanking period (line can be defined by nmline) 0: measurement in the active picture (first active line) subaddress 1e bit name function d7...d4 tnrcly temporal noise reduction of luminance: classification 1111: slight noise reduction : 0000: strong noise reduction d3...d0 tnrclc temporal noise reduction of chrominance: classification 1111: slight noise reduction : 0000: strong noise reduction subaddress 1f bit name function d7...d4 tnrkoy temporal noise reduction of luminance: vertical shift of the motion detector characteristic [tnrkoy=0 ]
micronas 59 preliminary data sheet sda 9401 d3...d0 tnrkoc temporal noise reduction of chrominance: vertical shift of the motion detector characteristic [tnrkoc=0 ] subaddress 20 bit name function d7...d4 tnrvay fixed k-factor for temporal noise reduction of luminance [tnrvay = 15 ] d3...d0 tnrvac fixed k-factor for temporal noise reduction of chrominance [tnrvac = 15 ] subaddress 21 bit name function d7...d2 tnrhoy temporal noise reduction of luminance: horizontal shift of the motion detector characteristic [tnrhoy=0 ] d1 tnrfiy fixed k-factor switch for temporal noise reduction of luminance: 1: off 0: on d0 should be set to 0 subaddress 22 bit name function d7...d2 tnrhoc temporal noise reduction of chrominance: horizontal shift of the motion detector characteristic [tnrhoc=0 ] d1 tnrfic fixed k-factor switch for temporal noise reduction of chrominance: 1: off 0: on d0 should be set to 0 subaddress 28 bit name function d7...d3 nmline line for noise measurement (only valid for nmalg=1) [nmline = 4 ] subaddress 1f bit name function
micronas 60 preliminary data sheet sda 9401 d2...d1 should be set to 01 d0 x x subaddress 32 bit name function d7...d3 noiseme noise level of the input signal: 0 (no noise), ..., 30 (strong noise) [31 (strong noise or measurement failed )] d2...d0 version version of sda 94xx family: 000: sda 9400 001: sda 9401 010: sda 9402 subaddress 33 bit name function d7...d5 xxx xxx d4 tvmode tv mode of the input signal 1: ntsc 0: pal d3 vistatus status bit for subaddresses, which will be made valid by vin 1: new write or read cycle can start 0: no new write or read cycle can start d2 osstatus status bit for subaddresses, which will be made valid by opstart 1: new write or read cycle can start 0: no new write or read cycle can start d1 x x d0 nmstatus status bit for noise measurement parameter: 1: new value of noiseme available 0: no new value of noiseme available subaddress ff bit name function d7...d0 store command for all subaddresses subaddress 28 bit name function
micronas 61 preliminary data sheet sda 9401 7 absolute maximum ratings all voltages listed are referenced to ground (0v, v ss ) except where noted. absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditions or at any other condition beyond those indicated in the operational sections of this specification is not implied. parameter symbol min max unit remark operating temperature t a 070 c storage temperature -65 125 c junction temperature 125 c soldering temperature 260 c soldering time 10 s input voltage -0.3 v dd +0.3 v not valid for i2c bus pins output voltage -0.3 v dd +0.3 v not valid for i2c bus pins input voltage -0.3 5.5 v i2c bus pins only output voltage -0.3 5.5 v i2c bus pins only supply voltages v dd -0.3 3.8 v total power dissipation 1 w esd protection -2,0 2,0 kv mil std 883c method 3015.6, 100pf, 1500 (hbm) esd protection -1,5 1,5 kv eos/esd assn. standard ds 5.3-1993 (cdm) latch-up protection -100 100 ma all inputs/outputs
micronas 62 preliminary data sheet sda 9401 8 recommended operating conditions parameter symbol min nom max unit remark supply voltages v dd 3.15 3.3 3.45 v ambient temperature t a 0 25 70 c all ttl inputs high-level input voltage v ih 2.0 v dd +0.2 v low-level input voltage v il -0.2 0.8 v input current i in +/- 5 a all ttl outputs high-level output voltage v oh 2.4 v i oh = -2.0 ma low-level output voltage v ol 0.4 v i ol = 2.0 ma input/output: sda low-level output voltage v ol 0.5 v at i ol = max clock ttl input clk1 clock frequency 1/t 27 mhz see diagr. 11.3 low time t wl 10 ns high time t wh 10 ns rise time t tlh 10 ns fall time t thl 10 ns input syncen low time t wl2 22 ns see diagr. 11.3 high time t wh2 22 ns rise time t tlh2 10 ns fall time t thl2 10 ns clock ttl input x1/clk2 clock frequency 1/t 27 mhz see diagr. 11.3 low time t wl 10 ns high time t wh 10 ns rise time t tlh 5ns fall time t thl 5ns i2c bus (all values are referred to min(v ih ) and max(v il )), f scl = 400 khz high-level input voltage v ih 3 5.25 v see diagr. 11.1 low-level input voltage v il 0 1.5 v see diagr. 11.2 scl clock frequency f scl 0 400 khz inactive time before start of transmission t buf 1.3 s set-up time start condition t su;sta 0.6 s
micronas 63 preliminary data sheet sda 9401 hold time start condition t hd;sta 0.6 s scl low time t low 1.3 s scl high time t high 0.6 s set-up time data t su;dat 100 ns hold time data t hd;dat 0s sda/scl rise times t r 300 ns sda/scl fall times t f 300 ns set-up time stop condition t su;sto 0.6 s output valid from clock t aa 900 ns input filter spike suppression (sda and scl pins) t sp 50 ns low-level output current i ql 3ma inputs crystal connections x1/clk2, x2 see diagr. 11.4 crystal frequency xtal 27.0 mhz fundamental crystal equivalent parallel capacitance cin 27 pf equivalent parallel capacitance cout 27 pf parameter symbol min nom max unit remark
micronas 64 preliminary data sheet sda 9401 9 characteristics (assuming recommended operating conditions) *: see also clock concept on page 27 parameter symbol min max unit remark average supply current t.b.d. t.b.d. ma all v dd pins, typ. t.b.d. ma all digital inputs (including i/o inputs) input capacitance 10 pf input leakage current -5 5 a ttl inputs: yin, uvin, hin, vin (referenced to clk1) set-up time t su 7 ns see diagr. 11.3 input hold time t ih 6ns ttl outputs: yout, uvout, href, interlaced (referenced to clkout*) hold time t oh 6 ns see diagr. 11.3 delay time t od 25 ns c l = 30 pf, 27 mhz ttl outputs: hout, vout (referenced to clkout) hold time t oh 6 ns see diagr. 11.3 delay time t od 25 ns c l = 50 pf, 27 mhz ttl inputs: syncen (referenced to clk1) set-up time t su 25 ns see diagr. 11.3 input hold time t ih 0ns
micronas 65 preliminary data sheet sda 9401 10 application information sda 9401 scarabaeus vpc32xxd color decoder ddp3310b deflection controller h-drive v-drive e/w cvbs y/c rgb r g b
micronas 66 preliminary data sheet sda 9401 11 waveforms 11.1 i2c-bus timing start/stop 11.2 i2c-bus timing data i2ctimd01 bus timing data i2ctimdat scl sda in sda out t sp t aa t aa t su;sta t hd;sta t f t high t low t hd;sta t su;dat t r t su;sto t buf
micronas 67 preliminary data sheet sda 9401 11.3 timing diagram clock 11.4 clock circuitry diagram v ih v il clk1 clkout t t wh t wl t hl t lh syncen t lh2 t hl2 t wl2 t wh2 datain datain dataout dataout t su t od t ih t oh t ih2 t su2 x1/clk2 x2 quartz xtal cin cout
micronas 68 preliminary data sheet sda 9401 12 package outlines p-mqfp-64 [all dimensions in mm]
all information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. any new issue of this data sheet invalidates previous issues. product availability and delivery are exclusively subject to our respective order confirmation form; the same applies to orders based on development samples deliv- ered. by this publication, micronas gmbh does not assume responsibil- ity for patent infringements or other rights of third parties which may result from its use. further, micronas gmbh reserves the right to revise this publication and to make changes to its content, at any time, without obligation to notify any person or entity of such revisions or changes. no part of this publication may be reproduced, photocopied, stored on a retrieval system, or transmitted without the express written consent of micronas gmbh. sda 9401 preliminary data sheet 69 micronas micronas gmbh hans-bunte-strasse 19 d-79108 freiburg (germany) p.o. box 840 d-79008 freiburg (germany) tel. +49-761-517-0 fax +49-761-517-2174 e-mail: docservice@micronas.com internet: www.micronas.com printed in germany order no. 6251-558-1pd

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